Additional PCIe capacity
Connect more devices, slots or modular chassis when the host platform alone is insufficient.
PCIe adapters, switches, chassis, modular interconnects and software for extending device capacity and building high-bandwidth data paths across hosts and chassis.
Select adapters, switches, modular interconnects, expansion chassis, link media and fabric software according to the required topology.
Connect a host to remote devices or another computer while choosing native transparent access or isolated NTB communication.
Scale port count, endpoint capacity and multi-host connectivity through MXS524 Gen5, MXS924 Gen4 and MXS824 Gen3 external switch platforms.
Expand modular systems, connect chassis to external compute and enable communication between independent controllers.
Add full-size and high-power devices with dedicated slots, cooling and service access while retaining the host platform.
Place PCIe resources across racks or rooms while preserving high-bandwidth access and using an electrically separated optical data path where appropriate.
Turn the hardware fabric into a usable application platform through shared memory, sockets, IP, device access and management.
The available products support several system approaches, from transparent device expansion to independent-host communication and direct device data paths.
Connect more devices, slots or modular chassis when the host platform alone is insufficient.
Retain compatible PCIe drivers, endpoint behaviour and DMA where the selected topology supports them.
Use NTB hardware and fabric software to exchange data between separate computers without merging their root complexes.
Select shared memory, sockets, IP, multicast or peer-to-peer transfers according to the application and supported hardware.
Dolphin Interconnect Solutions combines PCIe adapters, switches, modular-system interfaces and software for transparent I/O expansion, NTB communication and managed PCIe fabrics.
Transparent host and target adapters extend a root complex to compatible remote endpoints. Driver, BAR allocation, reset, hot-plug and peer-to-peer behaviour must be validated through the complete topology.
Non-transparent bridging keeps root complexes independent while enabling translated memory windows, DMA and interrupts. Switches add fan-out, multi-host and modular-system topologies.
Supported software components include SISCI, SuperSockets, IPoPCIe, reflective memory and SmartIO or device lending. Availability depends on the hardware family, operating system and license.
Current product families span PCIe Gen3, Gen4 and Gen5 adapters, PXIe and CompactPCI Serial modules, external switches and expansion systems. Model-specific links use SFF-8614, SFF-8644, CDFP CopprLink or FireFly optical interfaces; supported cable reach ranges from short passive-copper links to optical configurations of up to 200 metres.
Deployable patterns that define root-complex ownership, data movement, software responsibility, timing boundaries and qualification criteria before individual components are selected.
Extend native PCIe endpoints beyond the host while keeping one PCIe hierarchy and the endpoint driver model.
Explore architecture →Connect separate computers through NTB and select SISCI, SuperSockets or IPoPCIe according to the application path and supported software release.
Explore architecture →Distribute application-defined state to multiple nodes through SISCI broadcast segments and supported PCIe multicast.
Explore architecture →Route compatible acquisition, FPGA, GPU, NIC and NVMe transfers directly between local or remote endpoints to reduce host-memory staging.
Explore architecture →Scale slots and processing across chassis while keeping PCIe control/data transport separate from PXI timing and triggers.
Explore architecture →Pool compatible devices and expose them through Device Lending or SISCI SmartIO with explicit ownership and lifecycle control.
Explore architecture →PCIe interconnect is used where endpoint bandwidth, latency, native driver access or system scalability is a primary design constraint.
Increase accelerator and storage capacity while reducing data movement between compute, FPGA, GPU and NVMe stages.
Scale instruments and acquisition across chassis without replacing the complete controller and software environment.
Connect HIL, simulation, logging and accelerator platforms for high-rate validation workflows with defined latency and bandwidth.
Create direct camera, FPGA, GPU and storage pipelines that reduce host-copy overhead and processing delay.
Expand instrumentation and move device data efficiently into processing and storage for characterization and production test.
Build modular multi-node processing and remote-I/O systems with controlled ownership, isolation and deterministic data paths.